The trend in integrated circuits is toward higher performance, higher speed and lower cost. Correspondingly, device dimensions and element sizes are shrinking and gate dielectrics must scale accordingly. As physical gate dielectric thickness has decreased, the need for a higher dielectric constant and less leaky gate dielectric has arisen. In advanced metal oxide semiconductor field effect transistors (MOSFETs) nitrided silicon oxide layers are used as a gate dielectric. MOSFET transistors include a channel region formed in silicon, an N or P doped polysilicon gate formed on top of a thin gate dielectric layer and aligned over the channel region, and source/drain regions formed in the silicon on either side of the channel region.
However, a problem with nitrided silicon oxide layers is thickness variation across the wafer, particularly as the gate dielectric thickness decreases. Across wafer thickness variation of the gate dielectric leads directly to across wafer threshold voltage variation causing variations in performance of individual integrated circuit chips from the same wafer. Therefore, there is a need for a method of fabricating a nitrided silicon oxide layer having a relatively uniform across wafer thickness.